1. Field
The present disclosure relates generally to an interface between a host processor and a peripheral device such as a camera or sensor and, more particularly, to improving clock generation for single data rate data transfer on an N-wire communication interface.
2. Background
Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while the display for the cellular phone may be obtained from a second manufacturer. The application processor and a display or other device may be interconnected using a standards-based or proprietary physical interface. For example, a display may provide an interface that conforms to the Display System Interface (DSI) standard specified by the Mobile Industry Processor Interface Alliance (MIPI).
In one example, a multi-signal data transfer system may employ multi-wire differential signaling such as 3-phase or N-factorial (N!) low-voltage differential signaling (LVDS), transcoding (e.g., the digital-to-digital data conversion of one encoding type to another) may be performed to embed symbol clock information by causing a symbol transition at every symbol cycle, instead of sending clock information in separate data lanes (differential transmission paths). Embedding clock information by transcoding is an effective way to minimize skew between clock and data signals, as well as to eliminate the necessity of a phase-locked loop (PLL) to recover the clock information from the data signals.
Clock and data recovery (CDR) circuits are decoder circuits that extract data signals as well as a clock signals from multiple data signals. However, clock recovery from multiple data signals whose state transitions represent clock events often suffers unintended spike pulses on its recovered clock signal due to inter-lane skew of the data signals or glitch signals by intermediate or undeterminable data signal states at data transition times. For instance, such clock signal may be susceptible to jitter. Jitter is how early or late a signal transition is with reference to when it should transition. Jitter is undesirable because it causes transmission errors and/or limits the transmission speed. The recovered clock signal may be used to extract data symbols encoded within the multiple wires/conductors.
Therefore, a clock recovery circuit is needed that minimizes analog delays, is tolerant to jitter, and is scalable in multi-signal systems having different numbers of conductors.